Memory system provided with nand flash memory and method including simultaneously writing data to first and second districts

ABSTRACT

A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal, the first data written to the other of the memory cell arrays may be deleted or nullified.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2011-208105, filed Sep. 22, 2011,the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memorydevice, for example, a memory system provided with a NAND flash memory,and method of controlling the same.

BACKGROUND

Recently, memory capacity of a NAND flash memory has increased, and thenumber of word lines in one chip has also increased.

In writing of data, an error in part of bits in one page selected by oneword line can be corrected by using an error correction code (ECC).However, it is difficult to correct an error or omission in data inunits of pages by using an ECC.

Accordingly, heretofore, in order to protect data in units of pages,data identical to the data to be written is written to an area differentfrom the data to be written to thereby prepare a backup.

However, in order to record identical data such as the backup in adifferent area, it is necessary to write the identical data twice, andhence extra time has been required to write data, and the systemthroughput has been lowered. Thus, for this reason, a memory systemenabling data to be written securely at high speed is desired.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing a memory system appliedto an embodiment.

FIG. 2 is a block diagram showing part of FIG. 1.

FIG. 3 is a view showing an example of a command sequence according to afirst embodiment.

FIG. 4 is a view showing an example of a general command sequence.

FIG. 5 is a view shown to explain a write operation of first and seconddistricts.

FIG. 6 is a flowchart showing an operation of a second embodiment.

FIG. 7 is a flowchart showing an operation of a third embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory system includes first,and second districts, and control section. Each of the first and seconddistricts includes a memory cell array. The control section receives awrite command to simultaneously write first data to the first, andsecond districts, and addresses, and simultaneously writes the firstdata to the first and second districts.

Hereinafter, embodiments will be described with reference to thedrawings.

First Embodiment

FIG. 1 schematically shows a memory system according to this embodiment.

The memory system is constituted of a memory device 11 such as an SDcard, and host 20. It should be noted that the memory device 11 does notnecessarily has a card-like shape, and may be incorporated in the host20 in an undetachable manner. The host 20 is also called a host device.

Upon connection to the host 20, the memory device 11 receives powersupply to operate, and carries out processing corresponding to accessfrom the host 20. The memory device 11 includes a card controller 11 a.

The card controller 11 a is constituted of, for example, a hostinterface 12, CPU 13, read-only memory (ROM) 14, random access memory(RAM) 15, and buffer 16. These are connected to each other by a bus.Furthermore, a memory controller 17 is connected to the bus. Forexample, a NAND flash memory 18 is connected to the memory controller17.

The host interface 12 carries out interface processing between the cardcontroller 11 a and host 20.

The memory controller 17 carries out interface processing between thecard controller 11 a and NAND flash memory 18. Furthermore, the memorycontroller 17 includes an ECC circuit 17 a, and subjects data suppliedfrom the NAND flash memory 18 to error correction processing by means ofthe ECC circuit 17 a.

The CPU 13 controls operations of the whole memory device 11. The CPU 13receives a write command, read command, erase command, and the like fromthe host 20, and accesses an area on the NAND flash memory 18 orcontrols data transfer processing through the buffer 16.

The ROM 14 stores therein at least part of firmware such as a controlprogram or the like used by the CPU 13. The RAM 15 is used as a workarea of the CPU 13, and stores therein a control program, varioustables, and expanded register to be described later.

The buffer 16 temporarily stores therein a certain amount of data (forexample, data corresponding to one page) when data sent from the host 20is written to, for example, the NAND flash memory 18, or temporarilystores therein a certain amount of data when data read from the NANDflash memory is sent to the host 20.

The NAND flash memory 18 is constituted of, for example, a memory cellof the stacked gate structure or a memory cell of the MONOS structure.The NAND flash memory stores therein system software or the likeconfigured to control an operation of, for example, user data,application software or the card controller 11 a. The user data,application software, and system software are managed by a fileallocation table (FAT).

On the other hand, the host 20 can be applied to, for example, a digitalcamera, cellular phone, personal computer, and the like. The host 20 isconstituted of a host controller 21, CPU 22, ROM 23, RAM 24, and, forexample, hard disk 25 (including a solid state drive (SSD)). These areconnected to each other by a bus.

The CPU 22 controls the whole host. The ROM 23 stores therein firmwarenecessary for the operation of the CPU 22. Although the RAM 24 is usedas, for example, the work area of the CPU 22, a program which can beexecuted by the CPU 22 is also loaded here to be executed. The hard disk25 retains various data items. The host controller 21 carries outinterface processing between the host and memory device 11 in a statewhere the memory device is connected thereto. That is, the hostcontroller 21 issues various commands to be described later inaccordance with instructions of the CPU 22.

FIG. 2 shows an example of the NAND flash memory 18 shown in FIG. 1. TheNAND flash memory 18 is constituted of, for example, first and seconddistricts 31 a, and 31 b. The first and second districts 31 a and 31 bhave the identical configuration, and hence the first district 31 a willbe described and, in the second district 31 b, parts identical to thoseof the first district 31 a are denoted by identical reference symbols,and a description of them is omitted.

In the first district 31 a, a memory cell array 32 includes, as will bedescribed later, a plurality of blocks BLK0 to BLK4095. Each block isconstituted of a plurality of NAND strings. Each NAND string includes aplurality of memory cells MC connected in series, and selectiontransistors S1 and S2 configured to connect the NAND string to a bitline, and source line (not shown). A control gate of each memory cell isconnected to a word line WL.

Each word line WL is connected to row decoders 33 and 34, and a wordline is selected by the row decoders 33 and 34.

Further, each bit line BL is connected to a sense amplifier 35. Eachsense amplifier 35 is connected to each of a plurality of data registers36, 37, and 38, and a logic circuit 39. Each sense amplifier 35 detectsa voltage of the bit line BL at the time of write, verify, and read ofdata. The plurality of data registers 36, 37, and 38 hold data to bewritten to the memory cell at the time of write, and verify of the data,and hold data read from the memory cell at the time of read of the data.Each of the sense amplifiers 35, data registers 36, 37, and 38 is madeable to hold data of one page. The logic circuit 39 carries outoperations such as data transfer between the data registers 36, 37, and38, and data inversion or the like at the time of data write or dataread.

Furthermore, a peripheral circuit 40 is common-connected to the firstand second districts 31 a and 31 b. The peripheral circuit 40 includes,for example, an address decoder 41. The address decoder 41 is connectedto an IO pad 42, decodes an address supplied from the IO pad 42, andsupplies the decoded address to one of the first and second districts 31a and 31 b.

FIG. 3 shows an example of a command sequence according to the firstembodiment.

In the first embodiment, it is made possible to simultaneously write thesame data to the first and second districts 31 a and 31 b. Accordingly,a particular write command XX is defined. The symbol “XX” is anidentifier of the command, and is not limited to “XX”. It is sufficientif the identifier is a symbol or a numeral identifiable in the memorysystem.

Hereinafter, an operation to be carried out when the memory device 11receives a “command to duplex the same data to store” from the hostdevice 20 will be described below. The command to duplex the same datato store is input to the memory device 11 through the host interface 12.The CPU 13 interprets the command, and controls the NAND flash memory 18in such a manner that the memory controller 17 simultaneously writes thesame data to the first and second districts 31 a and 31 b.

Further, the host device 20 may attach a flag bit indicating that thedata is important, and requires secure protection to the data to beinput to the memory device 11. The CPU 13 interprets the flag bit, andcarries out control in such a manner that the memory controller 17simultaneously writes the same data to the first and second districts 31a and 31 b.

Further, when the host device 20 successively inputs the same data tothe memory device 11, the CPU may interpret this to carry out control insuch a manner that the memory controller 17 simultaneously writes thesame data to the first and second districts 31 a and 31 b.

The memory controller 17 first issues a command XX to simultaneouslywrite the same data to the first and second districts 31 a and 31 b tothe NAND flash memory 18 and, subsequently to this, outputs a pageaddress Add (L) in the first district 31 a. Subsequently, the memorycontroller 17 issues a command indicating that input of a page addressis to be successively carried out, such as a command to switch the firstor the second district 31 a or 31 b or a command 11 h (h indicates ahexadecimal number) to the NAND flash memory 18. Thereafter, the memorycontroller 17 supplies a page address Add (R) in the second district 31b, write data DT, and command 10 h in sequence to the NAND flash memory18. The command 10 h indicates, for example, the tail end of the commandsequence. When the command 10 h is issued, a ready/busy signal is setfrom a ready state to a busy state (B2R), and the data DT issimultaneously written to the page address Add (L) of the first district31 a, and page address Add (R) of the second district 31 b.

FIG. 4 shows a conventional command sequence. In the command sequenceshown in FIG. 3, after supplying the write command XX to write data tothe first and second districts 31 a and 31 b, and page addresses Add(L), and ADD (R) from the memory controller 17 to the memory device 11,the data DT has been supplied from the memory controller 17 to the NANDflash memory 18 only once.

On the other hand, in the general duplexing command sequence shown inFIG. 4, first the write command XX to simultaneously write the same datato the first and second districts 31 a and 31 b is issued, subsequentlythe address ADD (L), data DT, and command 11 h for the first district 31a are supplied to the NAND flash memory 18. After this, the memorycontroller 17 supplies in sequence the page address (R), and data DT forthe second district 31 b to the NAND flash memory 18, and then issuesthe command 10 h.

In the case of the command sequence shown in FIG. 4, it is necessary tosupply the same data DT twice from the memory controller 17 to the NANDFlash memory 18.

FIG. 5 shows a schematic operation to be carried out when the same datais written to the first and second districts 31 a and 31 b.

When the write command XX to write data to the first and seconddistricts 31 a and 31 b, and page addresses Add (L) and Add (R) aresupplied from the memory controller 17 to the NAND flash memory 18, theaddress decoder 41 supplies the page address Add (L) to the firstdistrict 31 a, and supplies the page address Add (R) to the seconddistrict 31 b. Further, the data DT supplied to the NAND flash memory 18is retained in a data register (XDL) 38 of each of the first and seconddistricts 31 a and 31 b. After this, the data retained in the dataregister 38 is transferred to each of the logic circuit 39, dataregisters 37 and 36, and sense amplifier 35, and is simultaneouslywritten to pages designated by the page addresses Add (L) and Add (R).

According to the above-mentioned first embodiment, the write command XXto write the same data DT to the first and second districts 31 a and 31b is defined, and the page addresses Add (L) and Add (R) of the firstand second districts 31 a and 31 b, and data DT are supplied in sequenceto the NAND flash memory 18 in response to the write command XX, wherebyit is possible to simultaneously write the same data to the first andsecond districts 31 a and 31 b. Accordingly, it is possible tosimultaneously write the same data to the first and second districts 31a and 31 b by the single write command XX and, unlike the conventionalcase, it is not necessary to transfer the same data twice. Accordingly,it is possible to improve the throughput of the write processing.

Further, the same data is simultaneously written to the first and seconddistricts 31 a and 31 b, and hence it is possible to reduce theprobability of the write data being destroyed. Accordingly, the commandsequence of this embodiment is effective when data difficult to bere-entered such as photographic data is to be securely preserved.

It should be noted that in this embodiment, although the case where theNAND flash memory 18 is provided with two districts has been described,the description can also be applied to a case where the NAND flashmemory 18 is provided with three or more districts in the same manner.Further, when the NAND flash memory 18 receives write data withoutpreparing the particular command to simultaneously write the same datato the first and second districts 31 a and 31 b, the same data may besimultaneously written to the first and second districts 31 a and 31 bat all times.

Second Embodiment

FIG. 6 shows a second embodiment, and shows, for example, an operationof a memory controller 17.

In the first embodiment, the same data DT is written to the first andsecond districts 31 a and 31 b by a single write command XX.

Conversely, in the second embodiment, immediately after the same data DTis written to first and second districts 31 a and 31 b, the data of oneof the first and second districts is read and, when the data is normal,the data which has been written to the other of the first and seconddistricts is nullified.

That is, when data is written to the NAND flash memory 18, if data writeis completed, status data indicating that data write has normally beencompleted is output from the NAND flash memory 18. However, even in thiscase, there occurs a case where data is destroyed with the advance ofdata write in the block. Whether or not the data is destroyed isdetermined by reading the data from the NAND flash memory 18. When thedata has normally been read, it is determined that the block in whichthe data is recorded is normal. Accordingly, the data of the districtincluding the block for which it is determined that the block is normalis left as it is, and the block including the same data in the otherdistrict is nullified.

More specifically, as shown in FIG. 6, in accordance with the firstembodiment, the same data DT is written to the first and seconddistricts 31 a and 31 b by the single write command XX (ST11).

After this, a read command to read the data DT written to one of thefirst and second districts 31 a and 31 b is issued from the memorycontroller 17. That is, for example, a read command to read the data DTwhich has been written to the first district 31 a is issued, and thedata DT which has been written to the first district 31 a is read(ST12).

The data DT read from the first district 31 a is transferred to thememory controller 17, and is subjected to the error correctionprocessing by the ECC circuit 17 a. As a result of the error correctionprocessing, it is determined whether or not the read data is normal.That is, it is determined whether or not an error included in the readdata is of such a degree that the error can be corrected (ST13).

When the error is of such a degree that the error can be corrected byusing the ECC circuit 17 a as a result of the determination, it isdetermined that the data DT read from the first district 31 a is normaldata, and the data of the other of the first and second districts 31 aand 31 b, i.e., in this case, the same data as that of the firstdistrict 31 a written to the second district 31 b is nullified (ST14).That is, the block of the second district 31 b, and including the samedata as that of the first district 31 a is nullified.

On the other hand, in step ST13 described above, when it is determinedthat the error of the read data is an uncorrectable error, a readcommand to read the data DT written to the other of the first and seconddistricts 31 a and 31 b, e.g., the second district 31 b is issued, andthe data DT written to the second district 31 b simultaneously with thefirst district 31 a is read (ST15).

The data DT read from the second district 31 b is transferred to thememory controller 17, and is subjected to the error correctionprocessing by the ECC circuit 17 a. As a result of the error correctionprocessing, it is determined whether or not the read data is normal.That is, it is determined whether or not the error included in the readdata is of such a degree that the error can be corrected (ST16).

When, as a result of the determination, the error is of such a degreethat the error can be corrected by the ECC circuit 17 a, it isdetermined that the data DT read from the second district 31 b is normaldata, and data of one of the first and second districts 31 a and 31 b,i.e., in this case, the block in which the same data must have beenwritten as that of the second district 31 b, and written to the firstdistrict 31 a is nullified (ST17).

Further, when, as a result of the determination of step ST16 describedabove, the error of the read data is an uncorrectable error, both theblocks of the first and second districts 31 a and 31 b each includingthe same data are erroneous, and hence the data is recognized as datawhich cannot be corrected even by this system (ST18).

It should be noted that regarding the nullification of the block carriedout by the memory controller 17, it is sufficient if, for example,access to the data is inhibited, and physically deleting the data is notnecessary. Further, deletion of data regarded as invalid data is carriedout by the memory controller 17 as the need arises.

According to the above-mentioned second embodiment, one of the dataitems DT written to the first and second districts 31 a and 31 b is readand, when the read data is normal, the block including the other of thedata items DT written to the first and second districts 31 a and 31 b isnullified. Accordingly, it is possible to securely write data to one ofthe first and second districts 31 a and 31 b by a single command.

For example, in the case where data is to be written to only one of thefirst and second districts 31 a and 31 b as in the conventional case,when the data write fails, although it is necessary for the memorycontroller 17 to issue a write command again, and transfer an addressand data to the memory device 11, there is a case where the data hasalready disappeared from the RAM 15. For example, when the host 20 is adigital still camera, photographed data is lost.

However, in the case of the second embodiment, the case where both thedata items written to both the first and second districts areerror-uncorrectable rarely occurs, and hence it is possible to securelywrite data, and improve the throughput of data write.

Moreover, when the data of one of the districts is normal, the block ofthe other of the districts including the same data is nullified, and isdeleted as the need arises, and hence it is possible to prevent thememory capacity from being reduced.

Third Embodiment

In the second embodiment, immediately after the same data is written toeach of the designated blocks of the first and second districts 31 a and31 b, a read command is issued from the memory controller 17 to readdata from a designated block of, for example, the first district 31 aand, when there is no error in the read data or when the error can becorrected by ECC processing, it is determined that the data of the firstdistrict 31 a is normal, and the block of the second district 31 bincluding the same data is nullified.

Conversely, in a third embodiment, immediately after the same data iswritten to each of first and second districts 31 a and 31 b, the writtendata is not read. In the case of the third embodiment, the data writtento each of the first and second districts 31 a and 31 b is regarded asbeing valid for the time being. That is, both the data items written tothe first and second districts 31 a and 31 b are treated as valid untilthe data item written to the first or second district 31 a or 31 b isread.

In this state, as shown in FIG. 7, upon receipt of a data read requestfrom a CPU 13 (ST21), a memory controller 17 first determines whether ornot the same data is written to the first and second districts 31 a and31 b (ST22). In this case, the memory controller 17 preserves, forexample, an issuance history of the write command XX, and pageaddresses, and the preserved page address and a read address arecompared with each other.

When, as a result of the above determination, the same data is writtento the first and second districts 31 a and 31 b, the operations of stepsST12 to ST18 shown in FIG. 6 are executed (ST23). That is, data is readfrom one of the first and second districts 31 a and 31 b. When the readdata is normal, the block including the same data recorded on the otherof the first and second districts 31 a and 31 b is nullified.

Further, when, as a result the determination of above step 22, it isdetermined that the same data is not written to the first and seconddistricts 31 a and 31 b, a normal read operation is executed (ST24).

According to the above-mentioned third embodiment, immediately afterdata is written to the first and second districts 31 a and 31 b, dataread configured to verify whether or not the written data is normal isnot carried out, and hence it is possible to reduce the overheadrequired for the verification. Accordingly, it is possible to enhancethe write speed.

It should be noted that in each of the above-mentioned first to thirdembodiments, the operation of the NAND flash memory including the firstand second districts has been described. However, the embodiments arenot limited to the above, and it is needless to say that the aboveembodiments can be applied to a NAND flash memory including three ormore districts.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1-13. (canceled)
 14. A memory system comprising: a flash memoryincluding first and second districts; and a memory controller includingan error correction circuit, wherein the memory controller is configuredto issue a write command to the flash memory to simultaneously writefirst data to both of the first and second districts, issue a readcommand to the flash memory to read the first data from one of the firstand second districts, and determine whether or not the first data readfrom the one of the first and second districts is correctable based on aresult of error correction in the error correction circuit, and thememory controller is configured to perform issuing the write command,and each of issuing the read command and determining whether or not thefirst data is correctable when executing a data write in reply to thewrite command.
 15. The system of claim 14, wherein when the first dataread from the one of the first and second districts is correctable, thememory controller is configured to instruct the internal controller todelete the first data written to the other of the first and seconddistricts.
 16. The system of claim 14, wherein upon receipt of a readinstruction from the external host device, the memory controller isconfigured to determine whether or not the first data has been writtento the first and second districts on the basis of a history of write tothe first and second districts and, when the first data has been writtento the first and second districts, reads the first data from one of thefirst and second districts.
 17. The system of claim 14, wherein thefirst district comprises: a first memory cell array including aplurality of memory cells; a first row decoder configured to select oneof the plurality of memory cells of the first memory cell array; and afirst sense amplifier configured to detect data read from the firstmemory cell array; and the second district comprises: a second memorycell array including a plurality of memory cells; a second row decoderconfigured to select one of the plurality of memory cells of the secondmemory cell array; and a second sense amplifier configured to detectdata read from the second memory cell array.
 18. The system of claim 14,wherein the internal controller includes an address decoder configuredto receive first and second addresses, supply the first address to thefirst district, and supply the second address to the second district.19. A memory system comprising: a flash memory including first andsecond districts; and a memory controller including an error correctioncircuit, wherein the memory controller writes first data to both of thefirst and second districts, and the memory controller, after writing thefirst data, reads the first data from one of the first and seconddistricts and determines the first data read from the one of the firstand second districts is correctable based on a result of errorcorrection in the error correction circuit.